X-Git-Url: http://repo.macrolet.net/gitweb/?a=blobdiff_plain;f=src%2Fcompiler%2Fx86-64%2Fvm.lisp;h=98d0f9b467ae8dd22c5692ed07f26331afa54f74;hb=127fd3d2fb843c6bb7ad0763e143d81877e760e8;hp=32a59d96d9e38c023df99ef715a8f7156e8b4ab6;hpb=0d871fd7a98fc4af92a8b942a1154761466ad8c9;p=sbcl.git diff --git a/src/compiler/x86-64/vm.lisp b/src/compiler/x86-64/vm.lisp index 32a59d9..98d0f9b 100644 --- a/src/compiler/x86-64/vm.lisp +++ b/src/compiler/x86-64/vm.lisp @@ -71,7 +71,7 @@ (defreg r15b 30 :byte) (defregset *byte-regs* al cl dl bl sil dil r8b r9b r10b - r11b #+nil r12b #+nil r13b r14b r15b) + #+nil r11b #+nil r12b r13b r14b r15b) ;; word registers (defreg ax 0 :word) @@ -116,8 +116,13 @@ ;; list of qword registers. However ;; r13 is already used as temporary [#lisp irc 2005/01/30] ;; and we're now going to use r12 for the struct thread* + ;; + ;; Except that now we use r11 instead of r13 as the temporary, + ;; since it's got a more compact encoding than r13, and experimentally + ;; the temporary gets used more than the other registers that are never + ;; wired. -- JES, 2005-11-02 (defregset *qword-regs* rax rcx rdx rbx rsi rdi - r8 r9 r10 r11 r14 r15) + r8 r9 r10 #+nil r11 #+nil r12 r13 r14 r15) ;; floating point registers (defreg float0 0 :float) @@ -224,8 +229,8 @@ ;; the non-descriptor stacks ;; XXX alpha backend has :element-size 2 :alignment 2 in these entries - (signed-stack stack) ; (signed-byte 32) - (unsigned-stack stack) ; (unsigned-byte 32) + (signed-stack stack) ; (signed-byte 64) + (unsigned-stack stack) ; (unsigned-byte 64) (character-stack stack) ; non-descriptor characters. (sap-stack stack) ; System area pointers. (single-stack stack) ; single-floats @@ -271,6 +276,8 @@ (character-reg registers :locations #!-sb-unicode #.*byte-regs* #!+sb-unicode #.*qword-regs* + #!+sb-unicode #!+sb-unicode + :element-size 2 #!-sb-unicode #!-sb-unicode :reserve-locations (#.al-offset) :constant-scs (immediate) @@ -382,15 +389,20 @@ `(progn ,@(forms))))) (def-misc-reg-tns unsigned-reg rax rbx rcx rdx rbp rsp rdi rsi - r8 r9 r10 r11 r12 r13 r14 r15) + r8 r9 r10 r11 r12 r13 r14 r15) (def-misc-reg-tns dword-reg eax ebx ecx edx ebp esp edi esi) (def-misc-reg-tns word-reg ax bx cx dx bp sp di si) (def-misc-reg-tns byte-reg al cl dl bl sil dil r8b r9b r10b - r11b r14b r15b) + r11b r12b r13b r14b r15b) (def-misc-reg-tns single-reg float0 float1 float2 float3 float4 float5 float6 float7 float8 float9 float10 float11 float12 float13 float14 float15)) +;; A register that's never used by the code generator, and can therefore +;; be used as an assembly temporary in cases where a VOP :TEMPORARY can't +;; be used. +(defparameter temp-reg-tn r11-tn) + ;;; TNs for registers used to pass arguments (defparameter *register-arg-tns* (mapcar (lambda (register-arg-name) @@ -485,3 +497,6 @@ (def!constant cfp-offset rbp-offset) ; pfw - needed by stuff in /code +(!def-vm-support-routine combination-implementation-style (node) + (declare (type sb!c::combination node) (ignore node)) + (values :default nil))