X-Git-Url: http://repo.macrolet.net/gitweb/?a=blobdiff_plain;f=src%2Fruntime%2Fmips-arch.c;h=72ac15afb7120b7a04eaaff05e70a610f6e1c545;hb=6ddc6bb305b4f218780d4b2c9a2ac3584a85f94a;hp=1d64f7649a53f1f57bb55da60f3d61d6a4b1d17f;hpb=79cc569a97e444389350ea3f5b1017374fe16bec;p=sbcl.git diff --git a/src/runtime/mips-arch.c b/src/runtime/mips-arch.c index 1d64f76..72ac15a 100644 --- a/src/runtime/mips-arch.c +++ b/src/runtime/mips-arch.c @@ -19,12 +19,13 @@ #include "interrupt.h" #include "interr.h" #include "breakpoint.h" -#include "monitor.h" #include "genesis/constants.h" +#define INSN_LEN sizeof(unsigned int) + void -arch_init() +arch_init(void) { return; } @@ -35,84 +36,205 @@ arch_get_bad_addr(int signam, siginfo_t *siginfo, os_context_t *context) /* Classic CMUCL comment: Finding the bad address on the mips is easy. */ - return (os_vm_address_t) siginfo->si_addr; + return (os_vm_address_t)siginfo->si_addr; } +static inline unsigned int +os_context_register(os_context_t *context, int offset) +{ + return (unsigned int)(*os_context_register_addr(context, offset)); +} + +static inline unsigned int +os_context_pc(os_context_t *context) +{ + return (unsigned int)(*os_context_pc_addr(context)); +} + +static inline unsigned int +os_context_insn(os_context_t *context) +{ + if (os_context_bd_cause(context)) + return *(unsigned int *)(os_context_pc(context) + INSN_LEN); + else + return *(unsigned int *)(os_context_pc(context)); +} + +boolean +arch_insn_with_bdelay_p(unsigned int insn) +{ + switch (insn >> 26) { + case 0x0: + switch (insn & 0x3f) { + /* register jumps */ + case 0x08: + case 0x09: + return 1; + } + break; + /* branches and immediate jumps */ + case 0x1: + switch ((insn >> 16) & 0x1f) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x10: + case 0x11: + case 0x12: + case 0x13: + return 1; + } + break; + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + return 1; + case 0x10: + case 0x11: + case 0x12: + switch ((insn >> 21) & 0x1f) { + /* CP0/CP1/CP2 branches */ + case 0x08: + return 1; + } + break; + /* branch likely (MIPS II) */ + case 0x14: + case 0x15: + case 0x16: + case 0x17: + return 1; + } + return 0; +} + +/* Find the next instruction in the control flow. For a instruction + with branch delay slot, this is the branch/jump target if the branch + is taken, and PC + 8 if it is not taken. For other instructions it + is PC + 4. */ static unsigned int -emulate_branch(os_context_t *context, unsigned int inst) +next_insn_addr(os_context_t *context, unsigned int inst) { unsigned int opcode = inst >> 26; unsigned int r1 = (inst >> 21) & 0x1f; unsigned int r2 = (inst >> 16) & 0x1f; unsigned int r3 = (inst >> 11) & 0x1f; unsigned int disp = ((inst&(1<<15)) ? inst | (-1 << 16) : inst&0x7fff) << 2; - unsigned int jtgt = (*os_context_pc_addr(context) & ~0x0fffffff) | (inst&0x3ffffff) << 2; - unsigned int tgt = *os_context_pc_addr(context); + unsigned int jtgt = (os_context_pc(context) & ~0x0fffffff) | (inst&0x3ffffff) << 2; + unsigned int tgt = os_context_pc(context); switch(opcode) { case 0x0: /* jr, jalr */ switch(inst & 0x3f) { case 0x08: /* jr */ - tgt = *os_context_register_addr(context, r1); + tgt = os_context_register(context, r1); break; case 0x09: /* jalr */ - tgt = *os_context_register_addr(context, r1); + tgt = os_context_register(context, r1); *os_context_register_addr(context, r3) - = *os_context_pc_addr(context) + 4; + = os_context_pc(context) + INSN_LEN; + break; + default: + tgt += INSN_LEN; break; } break; - case 0x1: /* bltz, bgez, bltzal, bgezal */ - switch((inst >> 16) & 0x1f) { + case 0x1: /* bltz, bgez, bltzal, bgezal, ... */ + switch(r2) { case 0x00: /* bltz */ - if(*os_context_register_addr(context, r1) < 0) + case 0x02: /* bltzl */ + if(os_context_register(context, r1) < 0) tgt += disp; + else + tgt += INSN_LEN; break; case 0x01: /* bgez */ - if(*os_context_register_addr(context, r1) >= 0) + case 0x03: /* bgezl */ + if(os_context_register(context, r1) >= 0) tgt += disp; + else + tgt += INSN_LEN; break; case 0x10: /* bltzal */ - if(*os_context_register_addr(context, r1) < 0) + case 0x12: /* bltzall */ + if(os_context_register(context, r1) < 0) { tgt += disp; - *os_context_register_addr(context, 31) - = *os_context_pc_addr(context) + 4; + *os_context_register_addr(context, 31) + = os_context_pc(context) + INSN_LEN; + } else + tgt += INSN_LEN; break; case 0x11: /* bgezal */ - if(*os_context_register_addr(context, r1) >= 0) + case 0x13: /* bgezall */ + if(os_context_register(context, r1) >= 0) { tgt += disp; - *os_context_register_addr(context, 31) - = *os_context_pc_addr(context) + 4; + *os_context_register_addr(context, 31) + = os_context_pc(context) + INSN_LEN; + } else + tgt += INSN_LEN; + break; + default: + tgt += INSN_LEN; break; } break; + case 0x2: /* j */ + tgt = jtgt; + break; + case 0x3: /* jal */ + tgt = jtgt; + *os_context_register_addr(context, 31) + = os_context_pc(context) + INSN_LEN; + break; case 0x4: /* beq */ - if(*os_context_register_addr(context, r1) - == *os_context_register_addr(context, r2)) + case 0x14: /* beql */ + if(os_context_register(context, r1) + == os_context_register(context, r2)) tgt += disp; + else + tgt += INSN_LEN; break; case 0x5: /* bne */ - if(*os_context_register_addr(context, r1) - != *os_context_register_addr(context, r2)) + case 0x15: /* bnel */ + if(os_context_register(context, r1) + != os_context_register(context, r2)) tgt += disp; + else + tgt += INSN_LEN; break; case 0x6: /* blez */ - if(*os_context_register_addr(context, r1) - <= *os_context_register_addr(context, r2)) + case 0x16: /* blezl */ + if(os_context_register(context, r1) + <= os_context_register(context, r2)) tgt += disp; + else + tgt += INSN_LEN; break; case 0x7: /* bgtz */ - if(*os_context_register_addr(context, r1) - > *os_context_register_addr(context, r2)) + case 0x17: /* bgtzl */ + if(os_context_register(context, r1) + > os_context_register(context, r2)) tgt += disp; + else + tgt += INSN_LEN; break; - case 0x2: /* j */ - tgt = jtgt; + case 0x10: + case 0x11: + case 0x12: + switch (r1) { + /* CP0/CP1/CP2 branches */ + case 0x08: + /* FIXME */ + tgt += INSN_LEN; + break; + } break; - case 0x3: /* jal */ - tgt = jtgt; - *os_context_register_addr(context, 31) - = *os_context_pc_addr(context) + 4; + default: + tgt += INSN_LEN; break; } return tgt; @@ -121,34 +243,28 @@ emulate_branch(os_context_t *context, unsigned int inst) void arch_skip_instruction(os_context_t *context) { - /* Skip the offending instruction */ - if (os_context_bd_cause(context)) { - /* Currently, we never get here, because Linux' support for - bd_cause seems not terribly solid (c.f os_context_bd_cause - in mips-linux-os.c). If a port to Irix comes along, this - code will be executed, because presumably Irix' support is - better (it can hardly be worse). We lose() to remind the - porter to review this code. -- CSR, 2002-09-06 */ - lose("bd_cause branch taken; review code for new OS?\n"); - *os_context_pc_addr(context) - = emulate_branch(context, *os_context_pc_addr(context)); - } else - *os_context_pc_addr(context) += 4; + /* Skip the offending instruction. Don't use os_context_insn here, + since in case of a branch we want the branch insn, not the delay + slot. */ + *os_context_pc_addr(context) + = (os_context_register_t) + next_insn_addr(context, + *(unsigned int *)(os_context_pc(context))); } unsigned char * arch_internal_error_arguments(os_context_t *context) { if (os_context_bd_cause(context)) - return (unsigned char *)(*os_context_pc_addr(context) + 8); + return (unsigned char *)(os_context_pc(context) + (INSN_LEN * 2)); else - return (unsigned char *)(*os_context_pc_addr(context) + 4); + return (unsigned char *)(os_context_pc(context) + INSN_LEN); } boolean arch_pseudo_atomic_atomic(os_context_t *context) { - return *os_context_register_addr(context, reg_ALLOC) & 1; + return os_context_register(context, reg_ALLOC) & 1; } void @@ -157,140 +273,153 @@ arch_set_pseudo_atomic_interrupted(os_context_t *context) *os_context_register_addr(context, reg_NL4) |= -1LL<<31; } -unsigned long +void +arch_clear_pseudo_atomic_interrupted(os_context_t *context) +{ + *os_context_register_addr(context, reg_NL4) &= ~(-1LL<<31); +} + +unsigned int arch_install_breakpoint(void *pc) { unsigned int *ptr = (unsigned int *)pc; - unsigned long result = (unsigned long) *ptr; + unsigned int insn; + + /* Don't install over a branch/jump with delay slot. */ + if (arch_insn_with_bdelay_p(*ptr)) + ptr++; - *ptr = (trap_Breakpoint << 16) | 0xd; - os_flush_icache((os_vm_address_t)ptr, sizeof(unsigned int)); + insn = *ptr; + *ptr = (trap_Breakpoint << 6) | 0xd; + os_flush_icache((os_vm_address_t)ptr, INSN_LEN); - return result; + return insn; +} + +static inline unsigned int +arch_install_after_breakpoint(void *pc) +{ + unsigned int *ptr = (unsigned int *)pc; + unsigned int insn; + + /* Don't install over a branch/jump with delay slot. */ + if (arch_insn_with_bdelay_p(*ptr)) + ptr++; + + insn = *ptr; + *ptr = (trap_AfterBreakpoint << 6) | 0xd; + os_flush_icache((os_vm_address_t)ptr, INSN_LEN); + + return insn; } void -arch_remove_breakpoint(void *pc, unsigned long orig_inst) +arch_remove_breakpoint(void *pc, unsigned int orig_inst) { unsigned int *ptr = (unsigned int *)pc; - *ptr = (unsigned int) orig_inst; - os_flush_icache((os_vm_address_t)ptr, sizeof(unsigned int)); + /* We may remove from a branch delay slot. */ + if (arch_insn_with_bdelay_p(*ptr)) + ptr++; + + *ptr = orig_inst; + os_flush_icache((os_vm_address_t)ptr, INSN_LEN); } +/* Perform the instruction that we overwrote with a breakpoint. As we + don't have a single-step facility, this means we have to: + - put the instruction back + - put a second breakpoint at the following instruction, + set after_breakpoint and continue execution. + + When the second breakpoint is hit (very shortly thereafter, we hope) + sigtrap_handler gets called again, but follows the AfterBreakpoint + arm, which + - puts a bpt back in the first breakpoint place (running across a + breakpoint shouldn't cause it to be uninstalled) + - replaces the second bpt with the instruction it was meant to be + - carries on + + Clear? */ + static unsigned int *skipped_break_addr, displaced_after_inst; static sigset_t orig_sigmask; void arch_do_displaced_inst(os_context_t *context, unsigned int orig_inst) { - unsigned int *pc = (unsigned int *)*os_context_pc_addr(context); - unsigned int *break_pc, *next_pc; - unsigned int next_inst; - int opcode; + unsigned int *pc = (unsigned int *)os_context_pc(context); + unsigned int *next_pc; orig_sigmask = *os_context_sigmask_addr(context); sigaddset_blockable(os_context_sigmask_addr(context)); - /* Figure out where the breakpoint is, and what happens next. */ - if (os_context_bd_cause(context)) { - break_pc = pc+1; - next_inst = *pc; - } - else { - break_pc = pc; - next_inst = orig_inst; - } - /* Put the original instruction back. */ - arch_remove_breakpoint(break_pc, orig_inst); - skipped_break_addr = break_pc; + arch_remove_breakpoint(pc, orig_inst); + skipped_break_addr = pc; /* Figure out where it goes. */ - opcode = next_inst >> 26; - if (opcode == 1 || ((opcode & 0x3c) == 0x4) || ((next_inst & 0xf00e0000) == 0x80000000)) - next_pc = (unsigned int *)emulate_branch(context, next_inst); - else - next_pc = pc+1; - - displaced_after_inst = arch_install_breakpoint(next_pc); + next_pc = (unsigned int *)next_insn_addr(context, *pc); + displaced_after_inst = arch_install_after_breakpoint(next_pc); } -static void -sigill_handler(int signal, siginfo_t *info, void *void_context) +void +arch_handle_breakpoint(os_context_t *context) { - os_context_t *context = arch_os_get_context(&void_context); - - fake_foreign_function_call(context); - monitor_or_something(); + handle_breakpoint(context); } -static void -sigtrap_handler(int signal, siginfo_t *info, void *void_context) +void +arch_handle_fun_end_breakpoint(os_context_t *context) { - os_context_t *context = arch_os_get_context(&void_context); - unsigned int code; - - code = ((*(int *) (*os_context_pc_addr(context))) >> 16) & 0x1f; - - switch (code) { - case trap_Halt: - fake_foreign_function_call(context); - lose("%%primitive halt called; the party is over.\n"); - - case trap_PendingInterrupt: - arch_skip_instruction(context); - interrupt_handle_pending(context); - break; - - case trap_Error: - case trap_Cerror: - interrupt_internal_error(signal, info, context, code==trap_Cerror); - break; - - case trap_Breakpoint: - handle_breakpoint(signal, info, context); - break; + *os_context_pc_addr(context) + = (os_context_register_t)(unsigned int) + handle_fun_end_breakpoint(context); +} - case trap_FunEndBreakpoint: - *os_context_pc_addr(context) = (int)handle_fun_end_breakpoint(signal, info, context); - os_flush_icache((os_vm_address_t)*os_context_pc_addr(context), sizeof(unsigned int)); - break; +void +arch_handle_after_breakpoint(os_context_t *context) +{ + arch_install_breakpoint(skipped_break_addr); + arch_remove_breakpoint((unsigned int *)os_context_pc(context), + displaced_after_inst); + *os_context_sigmask_addr(context) = orig_sigmask; +} - case trap_AfterBreakpoint: - arch_remove_breakpoint(os_context_pc_addr(context), displaced_after_inst); - displaced_after_inst = arch_install_breakpoint(skipped_break_addr); - *os_context_sigmask_addr(context) = orig_sigmask; - break; +void +arch_handle_single_step_trap(os_context_t *context, int trap) +{ + unsigned int code = *((u32 *)(os_context_pc(context))); + int register_offset = code >> 11 & 0x1f; + handle_single_step_trap(context, trap, register_offset); + arch_skip_instruction(context); +} - case 0x10: - /* Clear the pseudo-atomic flag */ - *os_context_register_addr(context, reg_NL4) &= ~(-1LL<<31); +static void +sigtrap_handler(int signal, siginfo_t *info, os_context_t *context) +{ + unsigned int code = (os_context_insn(context) >> 6) & 0xfffff; + /* FIXME: This magic number is pseudo-atomic-trap from parms.lisp. + * Genesis should provide the proper #define, but it specialcases + * pseudo-atomic-trap to work around some oddity on SPARC. + * Eventually this should go into handle_trap. */ + if (code==0x10) { + arch_clear_pseudo_atomic_interrupted(context); arch_skip_instruction(context); interrupt_handle_pending(context); - return; - - default: - interrupt_handle_now(signal, info, context); - break; - } + } else + handle_trap(context,code & 0x1f); } #define FIXNUM_VALUE(lispobj) (((int)lispobj) >> N_FIXNUM_TAG_BITS) static void -sigfpe_handler(int signal, siginfo_t *info, void *void_context) +sigfpe_handler(int signal, siginfo_t *info, os_context_t *context) { - unsigned int bad_inst; + unsigned int bad_inst = os_context_insn(context); unsigned int op, rs, rt, rd, funct, dest = 32; int immed; - unsigned int result; - os_context_t *context = arch_os_get_context(&void_context); - - if (os_context_bd_cause(context)) - bad_inst = *(unsigned int *)(*os_context_pc_addr(context) + 4); - else - bad_inst = *(unsigned int *)(*os_context_pc_addr(context)); + int result; op = (bad_inst >> 26) & 0x3f; rs = (bad_inst >> 21) & 0x1f; @@ -303,102 +432,106 @@ sigfpe_handler(int signal, siginfo_t *info, void *void_context) case 0x0: /* SPECIAL */ switch (funct) { case 0x20: /* ADD */ - /* FIXME: Hopefully, this whole section can just go away, - with the rewrite of pseudo-atomic and the deletion of - overflow VOPs */ - /* Check to see if this is really a pa_interrupted hit */ - if (rs == reg_ALLOC && rt == reg_NL4) { - *os_context_register_addr(context, reg_ALLOC) - += *os_context_register_addr(context, reg_NL4) &= ~(-1LL<<31); - arch_skip_instruction(context); - interrupt_handle_pending(context); - return; - } - result = FIXNUM_VALUE(*os_context_register_addr(context, rs)) - + FIXNUM_VALUE(*os_context_register_addr(context, rt)); + result = FIXNUM_VALUE(os_context_register(context, rs)) + + FIXNUM_VALUE(os_context_register(context, rt)); dest = rd; break; case 0x22: /* SUB */ - result = FIXNUM_VALUE(*os_context_register_addr(context, rs)) - - FIXNUM_VALUE(*os_context_register_addr(context, rt)); + result = FIXNUM_VALUE(os_context_register(context, rs)) + - FIXNUM_VALUE(os_context_register(context, rt)); dest = rd; break; + + default: + interrupt_handle_now(signal, info, context); + return; } break; case 0x8: /* ADDI */ - result = FIXNUM_VALUE(*os_context_register_addr(context,rs)) + (immed>>2); + result = FIXNUM_VALUE(os_context_register(context,rs)) + + (immed >> N_FIXNUM_TAG_BITS); dest = rt; break; - } - if (dest < 32) { - dynamic_space_free_pointer = - (lispobj *) *os_context_register_addr(context,reg_ALLOC); + default: + interrupt_handle_now(signal, info, context); + return; + } - *os_context_register_addr(context,dest) = alloc_number(result); + dynamic_space_free_pointer = + (lispobj *)(unsigned int)*os_context_register_addr(context,reg_ALLOC); - *os_context_register_addr(context, reg_ALLOC) = - (unsigned int) dynamic_space_free_pointer; + *os_context_register_addr(context,dest) = alloc_number(result); - arch_skip_instruction(context); + *os_context_register_addr(context, reg_ALLOC) = + (unsigned int) dynamic_space_free_pointer; - } - else - interrupt_handle_now(signal, info, context); + arch_skip_instruction(context); } -void -arch_install_interrupt_handlers() +unsigned int +arch_get_fp_control(void) { - undoably_install_low_level_interrupt_handler(SIGILL,sigill_handler); - undoably_install_low_level_interrupt_handler(SIGTRAP,sigtrap_handler); - undoably_install_low_level_interrupt_handler(SIGFPE,sigfpe_handler); -} + register unsigned int ret asm("$2"); -extern lispobj call_into_lisp(lispobj fun, lispobj *args, int nargs); + __asm__ __volatile__ ("cfc1 %0, $31" : "=r" (ret)); -lispobj -funcall0(lispobj function) -{ - lispobj *args = current_control_stack_pointer; + return ret; +} - return call_into_lisp(function, args, 0); +void +arch_set_fp_control(unsigned int fp) +{ + __asm__ __volatile__ ("ctc1 %0, $31" :: "r" (fp)); } -lispobj -funcall1(lispobj function, lispobj arg0) +void +arch_install_interrupt_handlers(void) { - lispobj *args = current_control_stack_pointer; + undoably_install_low_level_interrupt_handler(SIGTRAP,sigtrap_handler); + undoably_install_low_level_interrupt_handler(SIGFPE,sigfpe_handler); +} - current_control_stack_pointer += 1; - args[0] = arg0; +#ifdef LISP_FEATURE_LINKAGE_TABLE - return call_into_lisp(function, args, 1); -} +/* Linkage tables for MIPS -lispobj -funcall2(lispobj function, lispobj arg0, lispobj arg1) -{ - lispobj *args = current_control_stack_pointer; + Linkage entry size is 16, because we need 4 instructions to implement + a jump. The entry size constant is defined in parms.lisp. - current_control_stack_pointer += 2; - args[0] = arg0; - args[1] = arg1; + Define the register to use in the linkage jump table. For MIPS this + has to be the PIC call register $25 aka t9 aka reg_ALLOC. */ +#define LINKAGE_TEMP_REG reg_ALLOC - return call_into_lisp(function, args, 2); +/* Insert the necessary jump instructions at the given address. */ +void +arch_write_linkage_table_jmp(void* reloc_addr, void *target_addr) +{ + /* Make JMP to function entry. The instruction sequence is: + lui $25, 0, %hi(addr) + addiu $25, $25, %lo(addr) + jr $25 + nop */ + unsigned int *insn = (unsigned int *)reloc_addr; + unsigned int addr = (unsigned int)target_addr; + unsigned int hi = ((addr + 0x8000) >> 16) & 0xffff; + unsigned int lo = addr & 0xffff; + + *insn++ = (15 << 26) | (LINKAGE_TEMP_REG << 16) | hi; + *insn++ = ((9 << 26) | (LINKAGE_TEMP_REG << 21) + | (LINKAGE_TEMP_REG << 16) | lo); + *insn++ = (LINKAGE_TEMP_REG << 21) | 8; + *insn = 0; + + os_flush_icache((os_vm_address_t)reloc_addr, LINKAGE_TABLE_ENTRY_SIZE); } -lispobj -funcall3(lispobj function, lispobj arg0, lispobj arg1, lispobj arg2) +void +arch_write_linkage_table_ref(void *reloc_addr, void *target_addr) { - lispobj *args = current_control_stack_pointer; - - current_control_stack_pointer += 3; - args[0] = arg0; - args[1] = arg1; - args[2] = arg2; - - return call_into_lisp(function, args, 3); + *(unsigned int *)reloc_addr = (unsigned int)target_addr; } + +#endif