X-Git-Url: http://repo.macrolet.net/gitweb/?a=blobdiff_plain;f=src%2Fruntime%2Fmips-arch.c;h=72ac15afb7120b7a04eaaff05e70a610f6e1c545;hb=eac461c1f1ca91cfe282c779291d582ed6b336cb;hp=0c9be423b38ee6518ff10a7aa77c5371b09c7eda;hpb=5c4c126f50e6fb8184bf9ae4411d17327c24cb91;p=sbcl.git diff --git a/src/runtime/mips-arch.c b/src/runtime/mips-arch.c index 0c9be42..72ac15a 100644 --- a/src/runtime/mips-arch.c +++ b/src/runtime/mips-arch.c @@ -19,14 +19,13 @@ #include "interrupt.h" #include "interr.h" #include "breakpoint.h" -#include "monitor.h" #include "genesis/constants.h" #define INSN_LEN sizeof(unsigned int) void -arch_init() +arch_init(void) { return; } @@ -244,7 +243,7 @@ next_insn_addr(os_context_t *context, unsigned int inst) void arch_skip_instruction(os_context_t *context) { - /* Skip the offending instruction. Don't use os_context_insn here, + /* Skip the offending instruction. Don't use os_context_insn here, since in case of a branch we want the branch insn, not the delay slot. */ *os_context_pc_addr(context) @@ -274,13 +273,19 @@ arch_set_pseudo_atomic_interrupted(os_context_t *context) *os_context_register_addr(context, reg_NL4) |= -1LL<<31; } +void +arch_clear_pseudo_atomic_interrupted(os_context_t *context) +{ + *os_context_register_addr(context, reg_NL4) &= ~(-1LL<<31); +} + unsigned int arch_install_breakpoint(void *pc) { unsigned int *ptr = (unsigned int *)pc; unsigned int insn; - /* Don't install over a branch/jump with delay slot. */ + /* Don't install over a branch/jump with delay slot. */ if (arch_insn_with_bdelay_p(*ptr)) ptr++; @@ -321,7 +326,7 @@ arch_remove_breakpoint(void *pc, unsigned int orig_inst) os_flush_icache((os_vm_address_t)ptr, INSN_LEN); } -/* Perform the instruction that we overwrote with a breakpoint. As we +/* Perform the instruction that we overwrote with a breakpoint. As we don't have a single-step facility, this means we have to: - put the instruction back - put a second breakpoint at the following instruction, @@ -358,63 +363,59 @@ arch_do_displaced_inst(os_context_t *context, unsigned int orig_inst) displaced_after_inst = arch_install_after_breakpoint(next_pc); } -static void -sigtrap_handler(int signal, siginfo_t *info, void *void_context) +void +arch_handle_breakpoint(os_context_t *context) { - os_context_t *context = arch_os_get_context(&void_context); - unsigned int code = (os_context_insn(context) >> 6) & 0xfffff; - - switch (code) { - case trap_Halt: - fake_foreign_function_call(context); - lose("%%primitive halt called; the party is over.\n"); - - case trap_PendingInterrupt: - arch_skip_instruction(context); - interrupt_handle_pending(context); - break; - - case trap_Error: - case trap_Cerror: - interrupt_internal_error(signal, info, context, code == trap_Cerror); - break; + handle_breakpoint(context); +} - case trap_Breakpoint: - handle_breakpoint(signal, info, context); - break; +void +arch_handle_fun_end_breakpoint(os_context_t *context) +{ + *os_context_pc_addr(context) + = (os_context_register_t)(unsigned int) + handle_fun_end_breakpoint(context); +} - case trap_FunEndBreakpoint: - *os_context_pc_addr(context) - = (os_context_register_t)(unsigned int) - handle_fun_end_breakpoint(signal, info, context); - break; +void +arch_handle_after_breakpoint(os_context_t *context) +{ + arch_install_breakpoint(skipped_break_addr); + arch_remove_breakpoint((unsigned int *)os_context_pc(context), + displaced_after_inst); + *os_context_sigmask_addr(context) = orig_sigmask; +} - case trap_AfterBreakpoint: - arch_install_breakpoint(skipped_break_addr); - arch_remove_breakpoint((unsigned int *)os_context_pc(context), - displaced_after_inst); - *os_context_sigmask_addr(context) = orig_sigmask; - break; +void +arch_handle_single_step_trap(os_context_t *context, int trap) +{ + unsigned int code = *((u32 *)(os_context_pc(context))); + int register_offset = code >> 11 & 0x1f; + handle_single_step_trap(context, trap, register_offset); + arch_skip_instruction(context); +} - case 0x10: - /* Clear the pseudo-atomic flag */ - *os_context_register_addr(context, reg_NL4) &= ~(-1LL<<31); +static void +sigtrap_handler(int signal, siginfo_t *info, os_context_t *context) +{ + unsigned int code = (os_context_insn(context) >> 6) & 0xfffff; + /* FIXME: This magic number is pseudo-atomic-trap from parms.lisp. + * Genesis should provide the proper #define, but it specialcases + * pseudo-atomic-trap to work around some oddity on SPARC. + * Eventually this should go into handle_trap. */ + if (code==0x10) { + arch_clear_pseudo_atomic_interrupted(context); arch_skip_instruction(context); interrupt_handle_pending(context); - return; - - default: - interrupt_handle_now(signal, info, context); - break; - } + } else + handle_trap(context,code & 0x1f); } #define FIXNUM_VALUE(lispobj) (((int)lispobj) >> N_FIXNUM_TAG_BITS) static void -sigfpe_handler(int signal, siginfo_t *info, void *void_context) +sigfpe_handler(int signal, siginfo_t *info, os_context_t *context) { - os_context_t *context = arch_os_get_context(&void_context); unsigned int bad_inst = os_context_insn(context); unsigned int op, rs, rt, rd, funct, dest = 32; int immed; @@ -470,55 +471,67 @@ sigfpe_handler(int signal, siginfo_t *info, void *void_context) arch_skip_instruction(context); } -void -arch_install_interrupt_handlers() +unsigned int +arch_get_fp_control(void) { - undoably_install_low_level_interrupt_handler(SIGTRAP,sigtrap_handler); - undoably_install_low_level_interrupt_handler(SIGFPE,sigfpe_handler); -} + register unsigned int ret asm("$2"); -extern lispobj call_into_lisp(lispobj fun, lispobj *args, int nargs); + __asm__ __volatile__ ("cfc1 %0, $31" : "=r" (ret)); -lispobj -funcall0(lispobj function) -{ - lispobj *args = current_control_stack_pointer; + return ret; +} - return call_into_lisp(function, args, 0); +void +arch_set_fp_control(unsigned int fp) +{ + __asm__ __volatile__ ("ctc1 %0, $31" :: "r" (fp)); } -lispobj -funcall1(lispobj function, lispobj arg0) +void +arch_install_interrupt_handlers(void) { - lispobj *args = current_control_stack_pointer; + undoably_install_low_level_interrupt_handler(SIGTRAP,sigtrap_handler); + undoably_install_low_level_interrupt_handler(SIGFPE,sigfpe_handler); +} - current_control_stack_pointer += 1; - args[0] = arg0; +#ifdef LISP_FEATURE_LINKAGE_TABLE - return call_into_lisp(function, args, 1); -} +/* Linkage tables for MIPS -lispobj -funcall2(lispobj function, lispobj arg0, lispobj arg1) -{ - lispobj *args = current_control_stack_pointer; + Linkage entry size is 16, because we need 4 instructions to implement + a jump. The entry size constant is defined in parms.lisp. - current_control_stack_pointer += 2; - args[0] = arg0; - args[1] = arg1; + Define the register to use in the linkage jump table. For MIPS this + has to be the PIC call register $25 aka t9 aka reg_ALLOC. */ +#define LINKAGE_TEMP_REG reg_ALLOC - return call_into_lisp(function, args, 2); +/* Insert the necessary jump instructions at the given address. */ +void +arch_write_linkage_table_jmp(void* reloc_addr, void *target_addr) +{ + /* Make JMP to function entry. The instruction sequence is: + lui $25, 0, %hi(addr) + addiu $25, $25, %lo(addr) + jr $25 + nop */ + unsigned int *insn = (unsigned int *)reloc_addr; + unsigned int addr = (unsigned int)target_addr; + unsigned int hi = ((addr + 0x8000) >> 16) & 0xffff; + unsigned int lo = addr & 0xffff; + + *insn++ = (15 << 26) | (LINKAGE_TEMP_REG << 16) | hi; + *insn++ = ((9 << 26) | (LINKAGE_TEMP_REG << 21) + | (LINKAGE_TEMP_REG << 16) | lo); + *insn++ = (LINKAGE_TEMP_REG << 21) | 8; + *insn = 0; + + os_flush_icache((os_vm_address_t)reloc_addr, LINKAGE_TABLE_ENTRY_SIZE); } -lispobj -funcall3(lispobj function, lispobj arg0, lispobj arg1, lispobj arg2) +void +arch_write_linkage_table_ref(void *reloc_addr, void *target_addr) { - lispobj *args = current_control_stack_pointer; - - current_control_stack_pointer += 3; - args[0] = arg0; - args[1] = arg1; - args[2] = arg2; - - return call_into_lisp(function, args, 3); + *(unsigned int *)reloc_addr = (unsigned int)target_addr; } + +#endif