X-Git-Url: http://repo.macrolet.net/gitweb/?a=blobdiff_plain;f=src%2Fruntime%2Fppc-linux-os.c;h=443c733baeb7bdcfead22026ee70624bbfbf1a04;hb=df679ed627975948b1cee190f4d79c397588c43e;hp=c5dc7a29dd132bb38886645b3ee6f5f52780e3de;hpb=c1b4849c95bad4f3535fba2b9307fd37e15bcf6d;p=sbcl.git

diff --git a/src/runtime/ppc-linux-os.c b/src/runtime/ppc-linux-os.c
index c5dc7a2..443c733 100644
--- a/src/runtime/ppc-linux-os.c
+++ b/src/runtime/ppc-linux-os.c
@@ -38,10 +38,15 @@
 #include "validate.h"
 size_t os_vm_page_size;
 
-#if defined GENCGC		/* unlikely ... */
-#error SBCL PPC does not work with the GENCGC
-#include "gencgc.h"
-#endif
+struct thread *arch_os_get_current_thread() {
+    return all_threads;
+}
+int arch_os_thread_init(struct thread *thread) {
+    return 1;			/* success */
+}
+int arch_os_thread_cleanup(struct thread *thread) {
+    return 1;			/* success */
+}
 
 os_context_register_t   *
 os_context_register_addr(os_context_t *context, int offset)
@@ -67,7 +72,49 @@ os_context_sigmask_addr(os_context_t *context)
     return &context->uc_sigmask;
 }
 
-void os_flush_icache(os_vm_address_t address, os_vm_size_t length)
+unsigned long
+os_context_fp_control(os_context_t *context)
+{
+    /* So this may look like nice, well behaved code. However, closer
+       inspection reveals that gpr is simply the general purpose
+       registers, and PT_FPSCR is an offset that is larger than 32
+       (the number of ppc registers), but that happens to get the
+       right answer. -- CSR, 2002-07-11 */
+    return context->uc_mcontext.regs->gpr[PT_FPSCR]; 
+}
+
+void 
+os_restore_fp_control(os_context_t *context)
+{
+    unsigned long control;
+    
+    control = os_context_fp_control(context) & 
+      /* FIXME: Should we preserve the user's requested rounding mode?
+
+         Note that doing 
+
+	 ~(FLOAT_STICKY_BITS_MASK | FLOAT_EXCEPTIONS_BYTE_MASK)
+
+	 here leads to infinite SIGFPE for invalid operations, as
+	 there are bits in the control register that need to be
+	 cleared that are let through by that mask. -- CSR, 2002-07-16 */
+      FLOAT_TRAPS_BYTE_MASK;
+    
+    /* FIXME: Shoot me now.
+       
+       Hardcoded nastiness: the "0"s below refer to the first floating
+       point registers -- we should let gcc deal with that. The 8(31)
+       refers to the position on the stack, less one, of control (we
+       need for control to be the high word of the double loaded by
+       lfd; how do I know that r31 contains the stack? I don't, I'm
+       just guessing. The 255, on the other hand, is a valid constant
+       -- it says "move everything in the upper word into the floating
+       point control register. -- CSR, 2002-07-16 */
+    asm ("stw %0, 12(31); lfd 0, 8(31); mtfsf 255, 0" : : "r" (control) : "r31");
+}
+
+void 
+os_flush_icache(os_vm_address_t address, os_vm_size_t length)
 {
     /* see ppc-arch.c */
     ppc_flush_icache(address,length);