X-Git-Url: http://repo.macrolet.net/gitweb/?a=blobdiff_plain;f=src%2Fruntime%2Fppc-linux-os.c;h=c2dc0199e872b2367dfb2adec90659c9df5b2405;hb=bf40ae88bc289fd765a33861cc4bc0853ed483ba;hp=c4a30f6ef645e27d99ad39fcf5ea414e3c26bbd7;hpb=c65f4c06c83c9dbf213cece638ad3d59710841bb;p=sbcl.git diff --git a/src/runtime/ppc-linux-os.c b/src/runtime/ppc-linux-os.c index c4a30f6..c2dc019 100644 --- a/src/runtime/ppc-linux-os.c +++ b/src/runtime/ppc-linux-os.c @@ -18,6 +18,7 @@ #include #include #include +#include "sbcl.h" #include "./signal.h" #include "os.h" #include "arch.h" @@ -25,7 +26,6 @@ #include "interrupt.h" #include "interr.h" #include "lispregs.h" -#include "sbcl.h" #include #include @@ -34,6 +34,7 @@ #include #include #include +#include #include "validate.h" #include "ppc-linux-mcontext.h" @@ -41,10 +42,30 @@ size_t os_vm_page_size; int arch_os_thread_init(struct thread *thread) { - return 1; /* success */ +#if defined(LISP_FEATURE_SB_THREAD) + pthread_setspecific(specials,thread); +#endif + + /* For some reason, PPC Linux appears to default to not generating + * floating point exceptions. PR_SET_FPEXC is a PPC-specific + * option new in kernel 2.4.21 and 2.5.32 that allows us to + * configure this. Should we need to run on an older kenel, the + * equivalent trick is to get into a signal-handling context and + * modify the saved machine state register. + * + * PR_FP_EXC_PRECISE may be more accurate than we need, + * particularly if we move to the x86oid trick of inserting + * explicit synchronization for floating-point exception + * delivery. If we wish to move to such a model, the other two + * exception delivery modes that we could use are PR_FP_EXC_ASYNC + * and PR_FP_EXC_NONRECOV, and exception delivery can be forced + * by any access to the FPSCR. -- AB, 2010-May-23 */ + prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE, 0, 0); + + return 1; /* success */ } int arch_os_thread_cleanup(struct thread *thread) { - return 1; /* success */ + return 1; /* success */ } os_context_register_t * @@ -53,7 +74,7 @@ os_context_register_addr(os_context_t *context, int offset) #if defined(GLIBC231_STYLE_UCONTEXT) return &((context->uc_mcontext.regs)->gpr[offset]); #elif defined(GLIBC232_STYLE_UCONTEXT) - return &((context->uc_regs->gregs)[offset]); + return &((context->uc_mcontext.uc_regs->gregs)[offset]); #endif } @@ -63,7 +84,7 @@ os_context_pc_addr(os_context_t *context) #if defined(GLIBC231_STYLE_UCONTEXT) return &((context->uc_mcontext.regs)->nip); #elif defined(GLIBC232_STYLE_UCONTEXT) - return &((context->uc_regs->gregs)[PT_NIP]); + return &((context->uc_mcontext.uc_regs->gregs)[PT_NIP]); #endif } @@ -73,7 +94,35 @@ os_context_lr_addr(os_context_t *context) #if defined(GLIBC231_STYLE_UCONTEXT) return &((context->uc_mcontext.regs)->link); #elif defined(GLIBC232_STYLE_UCONTEXT) - return &((context->uc_regs->gregs)[PT_LNK]); + return &((context->uc_mcontext.uc_regs->gregs)[PT_LNK]); +#endif +} + +os_context_register_t * +os_context_ctr_addr(os_context_t *context) +{ + /* Like os_context_fp_control() and os_context_lr_addr(), this + * uses an index beyond the declared end of the array in order to + * find the correct register value in the context. */ +#if defined(GLIBC231_STYLE_UCONTEXT) + /* FIXME: This probably should be ->ctr instead of ->gpr[PT_CTR]. */ + return &((context->uc_mcontext.regs)->gpr[PT_CTR]); +#elif defined(GLIBC232_STYLE_UCONTEXT) + return &((context->uc_mcontext.uc_regs)->gregs[PT_CTR]); +#endif +} + +os_context_register_t * +os_context_cr_addr(os_context_t *context) +{ + /* Like os_context_fp_control() and os_context_lr_addr(), this + * uses an index beyond the declared end of the array in order to + * find the correct register value in the context. */ +#if defined(GLIBC231_STYLE_UCONTEXT) + /* FIXME: This probably should be ->ccr instead of ->gpr[PT_CCR]. */ + return &((context->uc_mcontext.regs)->gpr[PT_CCR]); +#elif defined(GLIBC232_STYLE_UCONTEXT) + return &((context->uc_mcontext.uc_regs)->gregs[PT_CCR]); #endif } @@ -83,7 +132,7 @@ os_context_sigmask_addr(os_context_t *context) #if defined(GLIBC231_STYLE_UCONTEXT) return &context->uc_sigmask; #elif defined(GLIBC232_STYLE_UCONTEXT) - return &context->uc_oldsigmask; + return &context->uc_sigmask; #endif } @@ -96,41 +145,33 @@ os_context_fp_control(os_context_t *context) (the number of ppc registers), but that happens to get the right answer. -- CSR, 2002-07-11 */ #if defined(GLIBC231_STYLE_UCONTEXT) - return context->uc_mcontext.regs->gpr[PT_FPSCR]; + return context->uc_mcontext.regs->gpr[PT_FPSCR]; #elif defined(GLIBC232_STYLE_UCONTEXT) - return context->uc_regs->gregs[PT_FPSCR]; + return context->uc_mcontext.uc_regs->gregs[PT_FPSCR]; #endif } -void +void os_restore_fp_control(os_context_t *context) { - unsigned long control; + /* KLUDGE: mtfsf has to be run against a float register, so we + * construct the float we need to use as an integer, then cast + * a pointer to its storage to a double and load that. For + * this to work, control must be the same width as a double, + * 64 bits. And why aren't we using a union here, anyway? */ + unsigned long long control; double d; - - control = os_context_fp_control(context) & - /* FIXME: Should we preserve the user's requested rounding mode? - - Note that doing - - ~(FLOAT_STICKY_BITS_MASK | FLOAT_EXCEPTIONS_BYTE_MASK) - - here leads to infinite SIGFPE for invalid operations, as - there are bits in the control register that need to be - cleared that are let through by that mask. -- CSR, 2002-07-16 */ - - FLOAT_TRAPS_BYTE_MASK; - + + /* FIXME: We are only preserving enabled traps and rounding + * mode here. Do we also want to preserve "fast mode"? */ + control = os_context_fp_control(context) & + (FLOAT_TRAPS_BYTE_MASK | FLOAT_ROUNDING_MODE_MASK); + d = *((double *) &control); - /* Hmp. Apparently the following doesn't work either: - asm volatile ("mtfsf 0xff,%0" : : "f" (d)); - - causing segfaults at the first GC. - */ } -void +void os_flush_icache(os_vm_address_t address, os_vm_size_t length) { /* see ppc-arch.c */