Microoptimization for code size in floating point comparisons on x86-64

Microoptimization for code size in floating point comparisons on x86-64

This affects EQL on real and complex floats and "=" on floats when at
least one of the two arguments is complex.

Use a 32-bit register as the destination of the MOVMSKP[SD] and the
source of the integer comparison instead of a 64-bit one. This doesn't
change the semantics but makes both instruction's encodings shorter.
If the register is EAX do the comparison on AL as this additionally
shortens the encoding.

Before:

  660F76C1         PCMPEQD XMM0, XMM1
  480F50C0         MOVMSKPS RAX, XMM0
  4883F80F         CMP RAX, 15

After:

  660F76C1         PCMPEQD XMM0, XMM1
  0F50C0           MOVMSKPS EAX, XMM0
  3C0F             CMP AL, 15